The present invention relates to the field of semiconductor device manufacturing, and more particularly, to the formation of low resistivity self-aligned silicide regions on the gate and source/drain junctions.
There is currently a desire to evaluate the use of selective epitaxial silicon in the manufacturing of semiconductor devices. The need for this technology is the xe2x80x9croadmapxe2x80x9d for silicon thickness on silicon-on-insulator (SOI) and the desire for faster parts on bulk silicon. The SOI roadmap suggests that the silicon thickness may be reduced to less than 500 xc3x85 in the near future. Assuming that each Angstrom of deposited cobalt (Co) in a conventional salicide process consumes approximately 3.5 xc3x85 of silicon from the substrate, a silicon thickness of 500 xc3x85 will be mostly consumed by the deposition and reaction of 100-130 xc3x85 of Co. Hence, the entirety and even the majority consumption of the silicon will deteriorate the transistor performance significantly. In addition, it is widely accepted that the elevation of the source and drain (or the reduction of silicon consumption) during silicidation is desirable for improving transistor performance, of either bulk or SOI devices.
A major difficulty with elevated source/drain technology is the actual elevating of the source/drains. The process must be selective and uniform, both of which pose difficult challenges. Selectivity means that the silicon must be grown epitaxially upon exposed silicon areas (source and drain), while not depositing on the exposed oxide or nitride regions. In addition, the silicon must be of uniform thickness across the wafer and across areas of differing patterning density. These constraints make the implementation of selective epitaxial silicon difficult. There are additional challenges as well. The process for selective epitaxial silicon involves the in-situ cleaning at elevated temperatures and deposition of silicon from a very reactive precursor. The deposition is sensitive to the condition of the silicon onto which the epitaxial silicon is grown. Thus, any surface damage from reactive chemical etching and/or ion implantation could be catastrophic and a difficult variable to control in the manufacturing of thousands of wafers per week. This makes the implementation of such a technology in actual production very challenging.
There are alternatives to selective epitaxial silicon that are being investigated. Once such technique is described in xe2x80x9cA Self-Aligned Silicide Process to Thin Silicon-On-Insulator MOSFETs and bulk MOSFETs with Shallow Junctionsxe2x80x9d, a manuscript submitted for publication to Materials Research Society (2001), from the IBM T. J. Watson Research Center, Cohen et al. In this alternative technique, Cohen et al. describes the modification of the salicide process to include co-sputtering of silicon with cobalt. After the reaction of this cobalt with the exposed silicon substrate in a conventional salicide process, a layer of amorphous silicon (a-Si) is deposited onto the exposed salicide and reacted with the Co2Si during formation of CoSi2. The source of silicon above the Co2Si helps reduce the silicon consumption from the substrate.
In U.S. Pat. No. 6,165,903, a method is described for forming ultra-shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation by supplying additional silicon during a salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high resistivity metal silicide regions are formed on the gate and source/drain junctions. Silicon is then deposited in a layer on the high resistivity metal silicide regions. An annealing step is then performed to form low resistivity metal silicide regions on the gate and source/drain junctions. The deposited silicon is a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide to a low resistivity metal silicide. Since the additional silicon provided in the deposited layer is consumed, there is reduced consumption of the silicon from the ultra-shallow junctions, thereby preventing the bottom of the silicide regions from reaching the bottom of the source/drain junctions.
Although the technique described in U.S. Pat. No. 6,165,903 may be considered a viable alternative to the process of selective epitaxial silicon on production wafers, improvements to the process are desirable in order to produce higher quality devices with reduced expenditures and with higher throughput. This would make the process even more commercially viable.
This and other needs are met by embodiments of the present invention which provide a method of forming ultra-shallow junctions in a semiconductor wafer, comprising the steps of forming gate and source/drain junctions having upper surfaces. First metal silicide regions are formed on the gate and source/drain junctions. These first metal suicide regions have a first resistivity. Amorphous silicon is deposited on the first metal silicide regions by plasma enhanced chemical vapor deposition (PECVD). Annealing is performed to form the second metal silicide regions with a second resistivity, lower than the first resistivity, by diffusion reaction of the first metal silicide region and the amorphous silicon.
The deposition of silicon by plasma enhanced vapor deposition (PECVD) provides a better uniformity than the PVD deposition processes, used in conventional technologies. The better uniformity of the amorphous silicon layer improves the device characteristics in performance of the product utilizing this technology. For example, the present invention provides a better uniform thickness across the wafers and across areas of differing patterning density.
In certain embodiments of the invention, the PECVD is performed at very low pressure with multiple layer deposition steps, utilizing multiple deposition stations.